1. Technical Field
The present invention relates to a protocol accelerator module for a data transmission protocol level of a transceiver, particularly but not exclusively for rapid forwarding of data packets in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard.
The invention also relates to a method of transceiver operation for rapid forwarding of data packets, likewise particularly, but not exclusively, in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard.
2. Discussion of Related Art
The IEEE 802.15.4 standard defines protocols for the first layer, i.e., the bit transmission layer, and for parts of the second layer, i.e. the media access layer of the data backup layer, of the ISO/OSI (International Standardization Organisation/Open Systems Interconnection) reference model.
Said standard supports wireless communication in a wireless network in which the transceiver of the network sends and receives data packets at data rates of up to 250 kilobits per second (kbps). It is particularly aimed at achieving a very low-complexity network structure that permits the participant transceivers to operate under battery power for several months and possibly even for several years due to the minimal system requirements. The distances between the respective transceivers of a network according to this standard are usually some meters, such as 10 m. The standard is used, for example, in sensor networks that are deployed in production automation technology or in interactive toys.
The structure of a network conforming to the IEEE 802.15.4 standard shall now be described in greater detail. In order to implement the IEEE 802.15.4 standard (IEEE Standard 802, “Part 15.4: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks,” 2006), a specially configured transceiver is provided—a “coordinator”, also referred to as a full function device (FFD) by those skilled in the art. A number of normally configured transceivers, referred to as reduced function devices (RFDs), are assigned to the coordinator.
The RFDs cannot communicate with each other directly, but only via the coordinator. The coordinator detects data packets that need to be forwarded and transmits these to the designated receiver or receivers. The coordinator may also comprise an interface to other data networks of whatever kind, for example to wireless networks such as Bluetooth or WLAN networks. In this connection it is also referred to as an “access point”.
In order to prevent collisions due to simultaneous transmission of several data packets, a time-division multiple access method (TDMA) is used, which may similarly be organized by the coordinator. To this end, the coordinator transmits “beacon data blocks” to all its associated RFDs at regular intervals, from which the RFDs can learn in which time slots they may transmit data packets. Only one transceiver may transmit data packets in a given time slot. Time slots are also allocated to the coordinator itself, of the kind that permit the transmission of the coordinator's own data packets, and of the kind provided for transmitting data packets that need to be forwarded. The latter time slots likewise contain the information about which receiver RFD the time slots is intended for.
In this standard, a data packet comprises a packet header and a data payload section. The packet header contains a maximum of two addresses, namely the transmitter and the immediate destination. The data payload is generally a few bytes in size. In order to prevent collisions between data packets, the standard also specifies alternative ways of organizing the TDMA method, in addition to the transmission of beacon data blocks by the coordinator.
In the protocol, it is also specified that all data packets to be transmitted are provided with an error detection code. A “cyclic redundancy check” (CRC) algorithm is used for this purpose, which calculates a checksum of all the bytes and places it at the end of the data packet. The recipients of the data packet calculate the CRC checksum on the basis of the received bytes and compare the result with the accompanying calculated value and sent in the data packet by the transmitter. When both checksums are identical, there is a very high probability that the data packet was correctly transmitted, otherwise an error is detected and the data packet is rejected.
The transmission of information from a first RFD (for example a sensor) to a second RFD (for example an actuator) therefore requires two time slots. In a first time slot, a data packet is transmitted from the first RFD to the coordinator, and in a second time slot, which need not follow immediately, the data packet is transmitted from the coordinator to the second RFD.
In order to forward the data packets, the coordinator must decode them, place them in an intermediate memory or buffer and prepare them for transmission in the correct time slot. In present-day applications of the aforementioned standard, part of the media access protocol (as well as the digital and analog signal processing) is realized in hardware, namely the functions of checking the data packet for transmission errors and adding an error checksum to the data payload, possibly also the functions of filtering the data packet on the basis of the address data in the packet header and automatically sending acknowledgement packets to the transmitter. A received data packet is stored in a transmit buffer to which a microcontroller can gain access. A software routine checks, inter alia, whether the data packet is one that needs to be forwarded. If this is affirmed, the data packet is transferred from the receive buffer to a transmit buffer. The data packets of the transmit buffer are transmitted on a “first in, first out” (FIFO) basis. Processing by the software is very time-consuming and involves an interrupt delay.
FIG. 1 shows a block diagram of the popular CC2420 single-chip transceiver made by TEXAS INSTRUMENTS and compliant with the IEEE 802.15.4 standard. It stands as an example for a number of other chips, such as the JN5139 made by JENNIC Ltd., the ML7065 made by OKI Semiconductor or the nRF2401A made by NORDIC Semiconductor, which provide the aforementioned hardware support for implementation of the media access protocol.
Whereas the signal propagation delay for the short distances between the RFDs is very short, and the data transmission times for data packets only a few bytes in size are also very short, the processing steps in the coordinator for forwarding data packets, in particular the steps that are implemented by software, are relatively time-consuming and stand in the way of a real-time connection between two or more RFDs. Transmission delays of many milliseconds can occasionally be expected. For many applications, this long transmission delay is not acceptable, since a rapid response to certain transmitted data packets may be desired. One can imagine, for example, a photoelectric barrier sensor (first RFD) and a stepper motor control (second RFD), in which the motor control must trigger a movement in response to signals from the photoelectric barrier sensor. In the context of this application, the expression “real-time connection” means that a system delivers a response to a stimulus within a defined period of time. This period may well amount to a number of minutes, depending on the system. For systems such as those mentioned above, for example in the field of production automation technology or interactive toys, the period is about a few milliseconds in duration.
The use of high-performance processors for shortening the interrupt delay caused by software is not a suitable approach due to the higher power consumption of the coordinator that this involves.
A protocol accelerator module for a data backup layer of transceiver is known from the German patent specification DE 10 2007 003 634 B3 filed by the present applicant, said module being configured, inter alia, to check that received data packets are received successfully and to trigger a memory operation in respect of said data packets, as well as to manage a queue of own data packets to be transmitted and to select data packets from the queue for transmission within an assigned transmission time slot and to transfer them to a transmitter unit.
Rapid forwarding of data cells is known from an asynchronous transfer mode (ATM) protocol for data transmission, a technology in which the forwarding function is performed by an ATM switch. In ATM switches, every incoming ATM data cell is guided from its input port to a predefined output port. On the output side, there is no need to pay attention to a suitable time slot or to the sender of the ATM data cells, since forwarding occurs on the basis of channel identifiers that are part of a given ATM data cell, and the assignment of channel identifiers to output ports is configured while a connection is established.
The disadvantage of prior art protocol accelerators is that they do not provide a function for accelerating data packet forwarding. The aforementioned protocol accelerators are therefore suitable to only a qualified extent for transceivers that adopt a coordinator role.
One object of the invention is therefore to propose a protocol accelerator module or a method of transceiver operation that permits rapid forwarding of data packets from second transceivers to third transceivers.